Reducing the size of semiconductor components is of crucial importance in the development of new generations of semiconductor technologies. By reducing the dimensions of the semiconductor components, it is possible to increase the integration density on a semiconductor chip and therefore to achieve a cost saving, which is an important development objective. However, insulation structures which provide an electrical insulation, for example between adjacent semiconductor components, in an ever smaller space are required in order to reduce the component dimensions.
The selective oxidation of silicon is an insulation process that is in widespread use in the field of silicon semiconductor technology. This is also referred to as LOCOS (LOCal Oxidation Of Silicon) and is used above all as suitable insulation between components.
A typical process sequence used to form LOCOS regions includes, for example, first of all growing a thermal oxide with a thickness of, for example, 50 nm on a silicon substrate, followed by subsequent production of a nitride layer with a thickness of, for example, 140 nm on the thermal oxide. The nitride layer on the thermal oxide can be patterned by means of a plasma etch. This uncovers the regions in which field oxide regions are to be formed during the subsequent oxidation. In the regions in which the nitride remains in place, the nitride acts as a barrier and prevents oxygen diffusion during the oxide growth. Since nitrogen-oxygen compounds also form on the nitride during the field oxidation, etching of the oxide is also required prior to the wet-chemical removal of the nitride mask, for example using phosphoric acid, but this involves undesirable thinning of the field oxide. On account of the lateral diffusion of the oxygen under the diffusion barrier nitride, the result is the “bird's beak” that is characteristic of a LOCOS structure. However, the dimensions of the bird's beak have to be taken into account in the design rules which are intended to ensure the process reliability and manufacturing suitability of a semiconductor technology, consequently resulting in relatively large fin and spacer regions. A fin with a typical lateral extent of 3.6 μm and a distance between adjacent LOCOS root points of 1.2 μm results for a LOCOS structure with a thickness of, for example, 600 nm. A reduction in the lateral dimensions of an insulation structure, for example in the case of a semiconductor technology with CMOS (Complementary Metal Oxide Semiconductor) and DMOS (Double Diffused Metal Oxide Semiconductor) components would have the effect of saving space during the formation of edge terminations, the separation between transistors, between highly doped n-type and p-type connection zones and between gate and drain regions.
In semiconductor technologies with features sizes in the range of 0.5 μm and below, what is known as shallow trench isolation (STI) constitutes another way of achieving higher integration densities of electrical insulation regions. A typical process sequence used to form a shallow trench isolation includes, for example, first of all anisotropically etching a trench into a semiconductor substrate, followed by thermal oxidation in order to oxidize out radiation damage. The trench is then filled, for example with the aid of a CVD oxide (CVD: chemical vapour deposition), e.g. with a HDPCVD oxide (high density plasma CVD oxide). The filling of the trench is followed by a planarization step, e.g. using CMP (Chemical Mechanical Polishing). Therefore, what remains is a trench which has been filled with oxide up to the surface of the semiconductor substrate. Shallow trench isolation can achieve smaller dimensions of the insulation structures compared to LOCOS insulation, but is associated with higher costs on account of the trench etch and the CMP.
For these and other reasons, there is a need for the present invention.